High sensitivity and wide dynamic range are key requirements for many imaging applications, but it is difficult to design a CMOS image sensor with very low read noise combined with high full well charge.
In a typical 3T or pinned photodiode (PPD) 4T pixel structure, the electrons are converted into voltage using a capacitor. The gain is determined from the equation:
  V  =            Q      C        =                  n        ⁢                  q          C                    =              n        ·        CVF            where V is the voltage, Q is the charge in coulombs, C is the capacitance of the conversion capacitor, q is elementary charge, n is the number of electrons, and CVF the conversion factor expressed in (micro)volt per electron. CVF is the measure for the voltage generated by one signal electron and is inversely proportional to the conversion capacitor C.
For low noise, a large conversion factor (CVF) is required. A large CVF reduces the impact of the typical dominant noise sources, being either the source follower or subsequent elements in the readout chain. Those noise sources are generated in the voltage domain, are expressed in volts, and, are, in first instance, not related to the CVF. However, their input related noise contribution expressed in electrons, scales down directly with CVF. To conclude, low noise means large CVF which means a small conversion capacitor needs to be provided.
However, the voltage on the conversion capacitor is limited by the supply voltage. Therefore, the larger the CVF, the fewer electrons fit on the conversion capacitor. A high CVF effectively thus limits the full well capacity, and it is difficult to obtain a satisfactory trade-off between high conversion gain and high full well capacity. This is also described in US-A-2005/0224843.
In an article by Nana Akahane, Satoru Adachi, Koichi Mizobuchi, and Shigetoshi Sugawa entitled “Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 11, NOVEMBER 2009, pages 2429 to 2435, a circuit is proposed in which both a high conversion gain and a full well capacity are achieved at the same time in a CMOS image sensor by utilising a lateral overflow integration capacitor. In particular, this article addresses the issues of limits for both high conversion gain and full well capacity as determined by the signal-to-noise ratio at a switching point between a low light signal and a bright light signal.
US-A-2008/0266434 discloses a pixel circuit in which an overflow capacitor is attached directly to a floating diffusion node via an additional transistor. This connection effectively raises the capacitance of the capacitor and hence limits the conversion factor. One problem with this approach is the inability to perform true correlated double sampling in combination with low frequency noise on the low gain channel if needed. The low gain reset sample would need to be taken at the start of the integration, the sample signal at the end of the integration gives rise to a large low frequency noise. Additionally, there is an inability to perform floating diffusion node sharing and low noise binning.
Similar problems arise in the circuitry described in US-A-2007/0278536, although one of the driving lines is switched off.
A dual transfer gate pixel arrangement is described in an article by Xinyang Wang, Bram Wolfs, Guy Meynants, and Jan Bogaerts, entitled “An 89 dB Dynamic Range CMOS Image Sensor with Dual Transfer Gate Pixel”, International Image Sensor Workshop 2011, Paper Number R36, in which low noise and high dynamic range is obtained in which the complete charge is transferred in one operation consisting of four steps depending on the level of illumination. The pixel arrangement comprises first and second floating diffusion regions, each region having a different conversion gain and its own dedicated transfer transistor, where the first floating diffusion region has a higher conversion gain than the second floating diffusion region and hence a lower capacity for receiving charge. The transfer ‘ON’ phase for the first transfer transistor is always activated first to allow charge to be transferred to the first floating diffusion region. For low levels of illumination where the first floating diffusion region has sufficient capacity to receive all the charge, there is no need to activate the second transfer transistor for the second floating diffusion region, and, on readout, the output signal is transferred from the first floating diffusion only. For high levels of illumination where the first floating diffusion becomes over-saturated (e.g., its capacity is not sufficient to receive all the charge from the pixel), both floating diffusion regions are utilised and the output signal is provided from the second floating diffusion region. In this latter case, the transfer ‘ON’ phase for each floating diffusion region is arranged to overlap. Again, the first transfer transistor is activated for the transfer ‘ON’ phase followed by the second transfer transistor to allow the remaining charge to be transferred to the second floating diffusion region of larger capacity. The first transfer resistor is then switched off and its charge is transferred to the second floating diffusion region. The second transfer transistor is switched off and the complete charge transfer operation is effected from the second floating diffusion region.
The conflict between high conversion gain and pixel saturation at low signal levels needs to be resolved.